This invention relates to semiconductor memory devices, and more particularly to an improved bit line and cell array structure for dynamic read/write memory devices.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams, and Redwine, or U.S. Pat. No. 4,293,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. Improvements in photolithography and semiconductor processing have made possible the 256K DRAM which is now available, and the 1-Megabit DRAM, now in development. All of these devices use a one-transistor storage cell in which the data is stored in a capacitor. In the devices of higher density, detecting the stored charge becomes more difficult because the cells are smaller and the bit line longer, with more cells per bit line. A reliable signal cannot be detected by a differential sense amplifier when the ratio is less than about 1/30 or 1/40; preferably the ratio is in the area of 1/20 or less.
Instead of the "open" bit line layout of U.S. Pat. Nos. 4,081,701 and 4,293,993, the two bit lines for a given sense amplifier may be folded to lie adjacent one another on the face of the chip. In this manner, locallized noise introduced into the substrate, as by alpha particles, for example, will be coupled equally to both bit lines and so will not affect the differential input to the sense amplifier. This folded bit line configuration can be detrimental to the capacitance ratio between storage capacitors and bit lines however, for some cell layouts, because the bit lines must be longer to accomodate twice the number of row lines on one side of a sense amplifier. That is, if the optimum cell width and length is such that a cell fits exactly with the pitch of bit lines and row lines for an open bit line configuration, then the same cell in a folded configuration will cause the bit lines to be longer, with more capacitance, because twice as many row lines must intercept a bit line.
It is the principal object of this invention to provide an improved bit line and cell array structure for high density dynamic RAM devices, particularly MOS devices using one-transistor cells. Another object is to provide a high density dynamic RAM in which the ratio of storage capacitance to bit line capacitance is a maximum, in a folded bit line layout.